A 16-bit/spl times/16-bit MAC design using fast 5:2 compressors

3:2 counters and/or 4:2 compressors have been widely used for multiplier implementations. In this paper, a new logical decomposition is derived for fast 5:2 compressor and is proposed to be used for 16-bit/spl times/16-bit MAC designs. In addition, when the accumulator output is in carry-save form, one row in partial product matrix can be eliminated prior to the partial product reduction process. These new methods are combined and explained with 16-bit/spl times/16-bit 2's complement MAC (multiply and accumulate) designs. The use of the new 5:2 compressor leads to 14% speed improvement in the MAC design over the conventional designs using 4:2 compressors and 3:2 counters.

[1]  Bruce A. Wooley,et al.  A Two's Complement Parallel Array Multiplication Algorithm , 1973, IEEE Transactions on Computers.

[2]  Kazuo Yano,et al.  A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .

[3]  Tohru Mogami,et al.  A 0.25-/spl mu/m CMOS 0.9-V 100-MHz DSP core , 1997 .

[4]  S. S. Rofail,et al.  A low-power 16/spl times/16-b parallel multiplier utilizing pass-transistor logic , 1999 .

[5]  Vojin G. Oklobdzija,et al.  A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach , 1996, IEEE Trans. Computers.

[6]  Takayasu Sakurai,et al.  A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications , 1996, IEEE J. Solid State Circuits.

[7]  Earl E. Swartzlander,et al.  Reduced area multipliers , 1993, Proceedings of International Conference on Application Specific Array Processors (ASAP '93).

[8]  O. L. Macsorley.  High-Speed Arithmetic in Binary Computers , 1961, Proceedings of the IRE.

[9]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[10]  Homayoon Sam,et al.  A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations , 1990, IEEE Trans. Computers.

[11]  Stamatis Vassiliadis,et al.  Hard-Wired Multipliers with Encoded Partial Products , 1991, IEEE Trans. Computers.

[12]  G. De Micheli,et al.  Circuit and architecture trade-offs for high-speed multiplication , 1991 .

[13]  Stamatis Vassiliadis,et al.  A General Proof for Overlapped Multiple-Bit Scanning Multiplications , 1989, IEEE Trans. Computers.

[14]  M. Nagamatsu,et al.  A 10 ns 54*54 b parallel structured full array multiplier with 0.5 mu m CMOS technology , 1991 .

[15]  Makoto Suzuki,et al.  A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer , 1995 .