Algorithmic Implementation of the Automated System of Gate-Level Simulation of Digital Circuits with Consideration of DF

An algorithm of logic simulation of digital circuits with consideration of destabilizing factors, preserving the advantages of well-known logic simulation algorithms and at the same time, providing consideration of all the features of the developed model of considering effects - the operation of signals with arbitrary amplitude and duration, change of timing parameters during simulation, etc. is described. Algorithms of mixed-mode simulation with consideration of destabilizing factors are also described, which ensure maximum independence of electrical and logic simulation.

[1]  Edwin Naroska.  Parallel VHDL simulation , 1998, Proceedings Design, Automation and Test in Europe.

[2]  Roger D. Chamberlain,et al.  Parallel Logic Simulation of VLSI Systems , 1995, 32nd Design Automation Conference.

[3]  David M. Lewis.  A hierarchical compiled code event-driven logic simulator , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Gustavo Deco,et al.  Finit Automata-Models for the Investigation of Dynamical Systems , 1997, Inf. Process. Lett..

[5]  Shyue-Kung Lu,et al.  Combinational circuit fault diagnosis using logic emulation , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[6]  Zhicheng Wang,et al.  LECSIM: a levelized event driven compiled logic simulation , 1991, DAC '90.

[7]  Carl Tropper,et al.  Scalable Clustered Time Warp and Logic Simulation , 1999, VLSI Design.

[8]  Sumit Ghosh,et al.  Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors , 1995, 32nd Design Automation Conference.

[10]  Peter Flake,et al.  An Algebra for Logic Strength Simulation , 1983, 20th Design Automation Conference Proceedings.

[11]  Roger D. Chamberlain,et al.  Parallel logic simulation of VLSI systems , 1994, CSUR.

[12]  M.H. Heydemann.  A Survey of MOS Logic Simulation Tools , 1983, ESSCIRC '83: Ninth European Solid-State Circuits Conference.

[13]  Jeff S. Steinman,et al.  SPEEDES - A multiple-synchronization environment for parallel discrete-event simulation , 1992 .

[14]  John P. Hayes,et al.  Digital Simulation with Multiple Logic Values , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Thomas Rauber,et al.  Scalability Analysis for Conservative Simulation of Logical Circuits , 1999, VLSI Design.

[16]  Alexander Miczo,et al.  Digital logic testing and simulation , 1986 .

[17]  Jack S. N. Jean,et al.  Concurrency Preserving Partitioning Algorithm for Parallel Logic Simulation , 1999, VLSI Design.

[18]  Peter Luksch.  Evaluation Of Three Approaches To Parallel Logic Simulation On A Distributed Memory Multiprocessor , 1993, [1993] Proceedings 26th Annual Simulation Symposium.