Finite Precision Analysis of FPGA-based Architecture for FBMC Transmultiplexers in Broadband PLC

Power-Line Communications (PLC) systems are becoming more and more relevant in certain environments since they take advantage of the infrastructure already installed to provide broadband data access. Previous proposals have developed different medium access techniques based on a Multi-Carrier Modulation (MCM) for the transmission of information, such as Filter-Bank Multi-Carrier (FBMC). These transmultiplexers present a receiver, where an equalizer is involved to compensate the effects coming from the PLC channel. Due to their high computational load, the definition of suitable hardware architectures for the real-time implementation of these proposals is still an ongoing issue. Currently, Field-Programmable Gate Array (FPGA) devices support implementations based on floating- or a fixed-point representation. This work presents an analysis between a fixed- and a floating-point architecture for the real-time implementation of a FBMC receiver, including an Adaptive SMFB/CMFB Equalizer for Transmultiplexers (ASCET), applied to broadband PLC. The study deals with every block from the FBMC scheme, analyzing which representation (fixed- or single floating-point) is more suitable in terms of performance and resource consumption. For that purpose, the Signal-Noise Ratio (SNR) and Root-Mean-Square Error (RMSE) for the whole system have been estimated. The final architecture has been particularized for a Zynq® UltraScale+™ device, taking into account the internal DSP cells and memory blocks.