An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source–drain extension, which simultaneously improves maximum frequency of oscillation ƒmax because of lower gate to drain capacitance, and intrinsic gain AV0 = gm-gds, due to lower output conductance gds. The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current Id on drain–source Vds and gate–source Vgs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (Jds∼10 µA-µm) improvement was observed in both third-order-intercept IIP3 (∼10 dBm) and intrinsic gain AV0 (∼20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of Id with respect to gate voltage and lower gds in FinFET compared to bulk MOSFET. Copyright © 2009 John Wiley & Sons, Ltd.

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