Design of a high performance pipelined transversal filter for fading channels equalization

A transversal filter with variable tap-gains is designed using a pipelined transposed architecture. An adaptive equalizer could be easily designed using this filter to mitigate distortion and provide diversity for mobile applications in time-varying fading channels. Also, different architectures for the implementation of the multipliers and the adders were compared with respect to the delay and area. The carry look-ahead with carry select was the architecture of choice for the adders and the Booth-coded Wallace tree architecture for the multipliers. The filter was implemented using an ASIC CMOS technology with a minimum feature of 0.5 /spl mu/m and the simulation results proved the design to be correctly functioning at frequencies up to 120 MHz with the power dissipation estimated to be around 756 mW. The chip can operate at much higher frequencies by making use of the state-of-the-art CMOS and packaging technologies.