Line edge roughness: characterization, modeling and impact on device behavior
暂无分享,去创建一个
W. Sansen | S. Decoutere | J. Croon | H. Maes | G. Storms | S. Winkelmeier | I. Pollentier | M. Ercken
[1] M.J.M. Pelgrom,et al. Matching properties of MOS transistors , 1989 .
[2] Marcel J. M. Pelgrom,et al. Transistor matching in analog CMOS applications , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[3] M. Ieong,et al. Modeling line edge roughness effects in sub 100 nanometer gate length devices , 2000, 2000 International Conference on Simulation Semiconductor Processes and Devices (Cat. No.00TH8502).
[4] K. Ronse,et al. Metrology method for the correlation of line edge roughness for different resists before and after etch , 2001 .
[5] C.H. Diaz,et al. An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.
[6] Andrew R. Brown,et al. Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs , 2001 .
[7] Investigation of Performance Improvement and Gate-to-junction Leakage Reduction for the 90nm CMOS Gate Stack Architecture , 2002, 32nd European Solid-State Device Research Conference.