Electro-thermal characterization of Through-Silicon Vias

Through-Silicon Vias (TSVs) are the vertial vias that enable three-dimensional integration by providing shorter, faster and denser interconnects. In this work, we investigate their thermal properties and show that TSVs used for power and ground connections can suffer from high thermal dissipations, which can lead to reliability and timing errors. Due to nature of current flow on 3D ICs (i.e. from package to each tier), we show that the TSVs near the package tier endure high current flows and high temperatures which eventually lead to Joule heating and electromigration (EM) phenomena. Such analyses bring forth the importance of power- and thermal-aware TSV placement.

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