Flexible Architecture Design for H.265/HEVC Inverse Transform

Highly-efficient video coding involves a great amount of computations. Hardware encoders apply different parallelization techniques to satisfy real-time requirements. This paper describes a novel design methodology for the 2D inverse transform used in the H.265/HEVC hardware decoder and encoder. To support different transform sizes, matrix multiplications are decomposed into some steps based on the division of transform blocks into fixed-size subblocks. The assumed order of processed subblocks along with separate transform cores assigned to both dimensions allows a significant reduction of the size of the transposition buffer, which in turn decreases the resource consumption of the whole architecture. The decomposition enables different hardware configurations of the architectures. Particularly, configuration parameters enable the tradeoff between resources and throughput, the interface adaptation to desired horizontal and vertical sizes, and the availability of particular transform sizes. Two versions of the architecture are developed for FPGA and ASIC technologies. Synthesis results show that they can operate at 200 and 400 MHz when implemented in FPGA Arria II and TSMC 90 nm, respectively.