Transient power supply current testing of digital CMOS circuits

This paper presents, in a tutorial fashion, a test technique that employs the transient power supply current, i/sub DDT/, as a window of observability into the switching behaviour of an integrated circuit. The premise is that when a circuit switches states, a temporary path is established between power and ground which results in a transient current. With proper power tree distribution, observing this transient current provides direct insight into the switching pattern of a circuit under a given stimulus. This paper includes an overall summary of physical experiments that have been conducted (previously reported in parts) as well as new results on the test overhead. The physical experimental results show i/sub DDT/ to be effective in detecting disturb faults in SRAMs and drain/ source opens in general CMOS logic structures.

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