An 18ns1mh Cmos Sram

RECENTLY, HIGH-DENSITY and high-speed SRAMs have been used as a main memory instead of DRAMS to improve the computer systems performance. For fhese RAM applications, density and access speed requirements have been increasing. This paper will describe an 1Mb (256K word x 4b) CMOS SRAM using a triple-polysilicon cell with a highly-resistive load. It has a typical address access time of 18ns, and an active power dissipation of 350mW. Performance has been achieved by using a sense amplifier with four stages, an aluminum word line, a 0 . 7 ~ gate transistor, and P-type substrate with an N-well CMOS process. This RAM utilizes a three-phase back-bias generator to stabilize the negative substrate-bias level.

[1]  Tetsuya Iizuka,et al.  A 25ns 1Mb CMOS SRAM , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[2]  S. Kayano,et al.  A 34ns 1Mb CMOS SRAM using triple poly , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[3]  Toshio Sasaki,et al.  A 42ns 1Mb CMOS SRAM , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  N. Hoshi,et al.  A 35ns 1Mb CMOS SRAM , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.