A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces

A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 mu m L/sub eff/, self-aligned TiSi/sub 2/ double-level metal, and an average minimum feature size of 1.35 mu m. Circuits keyed to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation including circuit-device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits are discussed. >

[1]  Hiep V. Tran,et al.  An 8ns Battery Back-Up Submicron Bicmos 256k Ecl Sram , 1988, 1988 IEEE International Solid-State Circuits Conference, 1988 ISSCC. Digest of Technical Papers.

[2]  R. L. Franch,et al.  A 6.2 ns 64Kb CMOS RAM with ECL interfaces , 1988, Symposium 1988 on VLSI Circuits.

[3]  Stanley E. Schuster,et al.  Fast CMOS ECL receivers with 100-mV worst-case sensitivity , 1988 .

[4]  Stanley E. Schuster,et al.  A 128k 6.5 ns access/5 ns cycle CMOS ECL static RAM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[5]  Yuan Taur,et al.  Submicrometer-channel CMOS for low-temperature operation , 1987, IEEE Transactions on Electron Devices.

[6]  Makoto Suzuki,et al.  A 7ns/350mW 64K ECL compatible RAM , 1987, 1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[7]  G. A. Sai-Halasz,et al.  Stability and SER analysis of static RAM cells , 1985 .

[8]  Peter W. Cook,et al.  A 15-ns CMOS 64K RAM , 1986 .