A first-order theory of the static induction transistor

Abstract A first-order theory of the static induction transistor (SIT) is proposed, which provides a unitary analytical description of its characteristics over the full range of normally encountered biasing conditions. The blocking-state and low-current analysis is based on the original modeling device of considering the intrinsic region of the SIT biased, across its boundary to the drain, by a cosine potential, the maximum value of which is set by a virtual intrinsic-drain electrode. The analytical development leads to design equations for specific SIT parameters such as barrier height, gate efficiency, voltage gain factor and forward blocking gain. The predicted low-current I - V characteristics are consistent with the reported experimental ones. Numerical over-relaxation calculations have been used for a spot-check verification of the analytical model, as well as for extracting the pertinent parameters of the extrinsic region. The intermediate- and high-current analysis of the intrinsic device reveals an interesting electrostatic feedback from the electronic charge in the channel, which carries the drain current, to the potential barrier which controls this current, resulting in triode-like I - V characteristics. The current flows within the limits of a neutral effective channel, which extends from the channel axis to the gates, as the drain current increases. This sets a drain current limitation for the linear range, corresponding to the situation when the channel is completely and uniformly filled with electrons, at the level of its doping concentration. The full-range I - V characteristic of the SIT is basically of the form i + ln i = v , where i and v are normalized drain current and equivalent gate voltage, respectively.

[1]  Bogdan M. Wilamowski,et al.  Interpretation of exponential type drain characteristics of the static induction transistor , 1980 .

[2]  W. Shockley.  The path to the conception of the junction transistor , 1976, IEEE Transactions on Electron Devices.

[3]  T. Ohmi,et al.  Punching through device and its integration—Static induction transistor , 1980, IEEE Transactions on Electron Devices.

[4]  R. J. Brewer.  The “barrier mode” behaviour of a junction FET at low drain currents , 1975 .

[5]  O. Ozawa,et al.  A vertical channel JFET fabricated using silicon planar technology , 1976, IEEE Journal of Solid-State Circuits.

[6]  B. J. Baliga.  High-voltage junction-gate field-effect transistor with recessed gates , 1982, IEEE Transactions on Electron Devices.

[7]  Bantval J. Baliga,et al.  A simple method for predicting the forward blocking gain of gridded field effect devices with rectangular grids , 1980 .

[8]  P. E. Gray,et al.  Electronic Principles: Physics, Models and Circuits , 1969 .

[9]  Y. Mochida,et al.  Characteristics of static induction transistors: Effects of series resistance , 1978, IEEE Transactions on Electron Devices.

[10]  H. Kodera,et al.  Optimum design of triode-like JFET's by two-dimensional computer simulation , 1977, IEEE Transactions on Electron Devices.

[11]  Potential, field and carrier distribution in the channel of junction field-effect transistors , 1970 .

[12]  J.D. Plummer,et al.  Small geometry depleted base bipolar transistors (BSIT)—VLSI devices? , 1981, IEEE Transactions on Electron Devices.

[13]  C. Bulucea,et al.  The field distribution and the critical field in surface-breakdown-limited planar silicon pn junctions , 1975 .

[14]  G. D. Alley,et al.  High-voltage two-dimensional simulations of permeable base transistors , 1983, IEEE Transactions on Electron Devices.

[16]  J. Nishizawa,et al.  Field-effect transistor versus analog transistor (static induction transistor) , 1975, IEEE Transactions on Electron Devices.

[17]  I. Bencuya,et al.  Static induction transistors optimized for high-voltage operation and high microwave power output , 1985, IEEE Transactions on Electron Devices.

[18]  B. J. Baliga,et al.  A power junction gate field-effect transistor structure with high blocking gain , 1980, IEEE Transactions on Electron Devices.

[19]  R. R. O'Brien,et al.  Computer aided two-dimensional analysis of the junction field-effect transistor , 1970 .

[20]  S. Teszner.  Gridistor development for the microwave power region , 1972 .

[21]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[22]  C. Bulucea,et al.  Surface breakdown in silicon planar junctions—A computer-aided experimental determination of the critical field , 1974 .

[23]  The spatial variation of the quasi-Fermi potentials in reverse-biased p + -n junctions and its implications in transition region capacitance calculations , 1969 .

[24]  D. Estève,et al.  ENTIRELY DIFFUSED VERTICAL CHANNEL JFET: THEORY AND EXPERIMENT , 1978 .

[25]  R. Zuleeg,et al.  A silicon space-charge-limited triode and analog transistor , 1967 .

[26]  C. Jacoboni,et al.  A review of some charge transport properties of silicon , 1977 .

[27]  A vertical FET with self-aligned ion-implanted source and gate regions , 1978, IEEE Transactions on Electron Devices.

[28]  M. Kato,et al.  Characteristics of high-power and high-breakdown-voltage static induction transistor with the high maximum frequency of oscillation , 1982, IEEE Transactions on Electron Devices.

[29]  G. D. Alley,et al.  Fabrication and numerical simulation of the permeable base transistor , 1980, IEEE Transactions on Electron Devices.