In this paper we present a technique allowing to transform any RAM test algorithm to a transparent BlST algorithm. The interest of such algorithms is that at the end of the test session the contents of the RAM are equal to its initial contents. Thus the transparent BlST is very suitable for periodic testing. Our transparent BlST algorithms does not decrease the fault coverage of the initial algorithms and involve a slightly greater area overhead than the standard BIST. Thus the transparent BlST becomes more attractive than the standard BlST since it can be used for both fabrication testing and periodic testing. In this paper we propose a transparent BlST technique. That is to say a BlST technique which preserves the initial contents of the RAM. The pioneering work on RAM transparent BlST is presented by B. Koeneman in the 1986 DFT workshop. In our knowledge this is the only existing work on this field. Our technique has the advantage that it can be applied to any test algorithm. Also the Koeneman's technique can be used only with linear compaction schemes while our technique can be used with any compaction scheme. We also illustrate that the Koeneman's signature verification technique may involve error masking, while this does not happens with our technique. Finally, we give a simple criterion allowing to verify if the fault coverage is preserved by the transparent test algorithms. It consists on checking if some symmetric property is verified by the fault model. We show that this property is verified by all the complete RAM fault models. For the more of the known reduced RAM fault models (i.e. fault models which do not include the whole set of a given type of faults), the fault coverage is preserved too. But for some reduced fault models the reduction breaks the symmetry and the fault coverage can be decreased. We also have illustrated that the transparent BET technique requires a slightly more complex circuitry than the standard BET techniques. Thus it becomes more attractive than the standard BlST since it allows to perform both fabrication testing and periodic testing.
[1]
John P. Hayes.
Testing Memories for Single-Cell Pattern-Sensitive Faults
,
1980,
IEEE Transactions on Computers.
[2]
Bernard Courtois,et al.
Built-in self-test in multi-port RAMs
,
1991,
1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.
[3]
Kozo Kinoshita,et al.
Test Pattern Generation for API Faults in RAM
,
1985,
IEEE Transactions on Computers.
[4]
Sudhakar M. Reddy,et al.
A March Test for Functional Faults in Semiconductor Random Access Memories
,
1981,
IEEE Transactions on Computers.
[5]
Michael Nicolaidis,et al.
A tool for automatic generation of BISTed and transparent BISTed RAMs
,
1992,
Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.
[6]
Christos A. Papachristou,et al.
An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories
,
1985,
IEEE Transactions on Computers.
[7]
Marian Marinescu,et al.
Simple and Efficient Algorithms for Functional RAM Testing
,
1982,
ITC.
[8]
Jacob A. Abraham,et al.
TESTING OF SEMICONDUCTOR RANDOM ACCESS MEMORIES.
,
1977
.
[9]
Ad J. van de Goor,et al.
An overview of deterministic functional RAM chip testing
,
1990,
CSUR.
[10]
Sudhakar M. Reddy,et al.
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories
,
1980,
IEEE Transactions on Computers.
[11]
Jacob A. Abraham,et al.
Efficient Algorithms for Testing Semiconductor Random-Access Memories
,
1978,
IEEE Transactions on Computers.