A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC

This work proposes an SRAM-based mixed-signal in-memory computing macro using a pseudo-differential voltage-mode accumulator and a row-by-row ADC. The macro consists of 128 parallel mixed-signal dot-product computing units, each with 128 bitcells (64 for synapses, 32 for ADC reference, and 32 for offset calibration). A bitcell comprises of a 6T SRAM cell, an XNOR-based binary multiplier, and a pseudo-differential voltage -mode driver. A 65nm test-chip is fabricated, and the measured energy efficiency is 87TOPS/W with 5bit ADC at 0.5V supply.