Area Efficient Fft/Ifft Processor for Wireless Communication

Fast Fourier Transform (FFT) processing is one of the key procedures in popular Orthogonal Frequency Division Multiplexing (OFDM) communication systems. Structured pipeline architectures, low power consumption, high speed and reduced chip area are the main concerns in this VLSI implementation. In this paper, the efficient implementation of FFT/IFFT processor for OFDM applications is presented. The processor can be used in various OFDM-based communication systems, such as worldwide interoperability for Microwave access (Wi-Max), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVBT). We adopt single-path delay feedback architecture. To eliminate the Read Only Memories (ROM’s) used to store the twiddle factors, this proposed architecture applies a reconfigurable complex multiplier to achieve a ROM-less FFT/IFFT processor and to reduce the truncation error we adopt the fixed width modified booth multiplier. The three Processing Elements (PE’s), Delay-Line (DL) buffers are used for computing IFFT. Thus we consume the low power, lower hardware cost, and high efficiency and reduced chip size.