GCS: High-performance gate-level simulation with GPGPUs

In recent years, the verification of digital designs has become one of the most challenging, time consuming and critical tasks in the entire hardware development process. Within this area, the vast majority of the verification effort in industry relies on logic simulation tools. However, logic simulators deliver limited performance when faced with vastly complex modern systems, especially synthesized netlists. The consequences are poor design coverage, delayed product releases and bugs that escape into silicon. Thus, we developed a novel GPU-accelerated logic simulator, called GCS, optimized for large structural netlists. By leveraging the vast parallelism offered by GP-GPUs and a novel netlist balancing algorithm tuned for the target architecture, we can attain an order-of-magnitude performance improvement on average over commercial logic simulators, and simulate large industrial-size designs, such as the OpenSPARC processor core design.

[1]  Young-Il Kim,et al.  Communication-efficient hardware acceleration for fast functional simulation , 2004, Proceedings. 41st Design Automation Conference, 2004..

[2]  Atchuthan S Perinkulam.  Logic Simulation Using Graphics Processors , 2007 .

[3]  Janick Bergeron,et al.  Writing Testbenches: Functional Verification of HDL Models , 2000 .

[4]  Sunil P. Khatri,et al.  Towards acceleration of fault simulation using Graphics Processing Units , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[5]  Valeria Bertacco,et al.  Event-driven gate-level simulation with GP-GPUs , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[6]  Yervant Zorian,et al.  2003 technology roadmap for semiconductors , 2004, Computer.

[7]  Jacob A. Abraham,et al.  Distributed VLSI simulation on a network of workstations , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[8]  Yangdong Deng,et al.  Taming irregular EDA applications on GPUs , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[9]  H. Pape,et al.  Code verification by hardware acceleration , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).

[10]  Sunil P. Khatri,et al.  Accelerating statistical static timing analysis using graphics processing units , 2009, 2009 Asia and South Pacific Design Automation Conference.

[11]  Yervant Zorian,et al.  2001 Technology Roadmap for Semiconductors , 2002, Computer.

[12]  Tom Blank,et al.  Parallel logic simulation on general purpose machines , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[13]  Soon Myoung Chung,et al.  Parallel logic simulation using Time Warp on shared-memory multiprocessors , 1994, Proceedings of 8th International Parallel Processing Symposium.

[14]  Edward H. Frank.  Exploiting Parallelism in a Switch-Level Simulation Machine , 1986, 23rd ACM/IEEE Design Automation Conference.

[15]  Ausif Mahmood,et al.  Parallel event-driven logic simulation algorithms: tutorial and comparative evaluation , 1996 .

[16]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[17]  David M. Lewis.  A hierarchical compiled code event-driven logic simulator , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Sunil P. Khatri,et al.  Fault table generation using Graphics Processing Units , 2009, 2009 IEEE International High Level Design Validation and Test Workshop.

[19]  M.M. Denneau.  The Yorktown Simulation Engine , 1982, 19th Design Automation Conference.

[20]  Anant Agarwal,et al.  Logic emulation with virtual wires , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Wolfgang Roesner,et al.  Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon) , 2005 .

[22]  Gerd Meister.  A Survey on Parallel Logic Simulation , 1993 .

[23]  Y. Matsumoto,et al.  Parallel logic simulation on a distributed memory machine , 1992, [1992] Proceedings The European Conference on Design Automation.

[24]  Barry K. Rosen,et al.  HSS--A High-Speed Simulator , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[25]  Naraig Manjikian,et al.  High performance parallel logic simulations on a network of workstations , 1993, PADS '93.

[26]  Randal E. Bryant,et al.  COSMOS: a compiled simulator for MOS circuits , 1987, DAC '87.

[27]  Yici Cai,et al.  GPU friendly Fast Poisson Solver for structured power grid network analysis , 2009, 2009 46th ACM/IEEE Design Automation Conference.