Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration
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C. Fenouillet-Béranger | R. Beneyton | J. Mazurier | D. Benoit | D. Barge | C. Gaumer | S. Chhun | S. Lagrasta | O. Hinsinger | D. Galpin | D. Vo-Thanh | R. Duru | B. van Schravendijk | B. Varadarajan | N. Sun | B. Gong | N. Chauvet | P. Ruault | D. Winandy | P. Meijer