Power Considerations in Banked CAMs: A Leakage Reduction Approach
暂无分享,去创建一个
[1] Hisatada Miyatake,et al. A design for high-speed low-power CMOS fully parallel content-addressable memory macros , 2001 .
[2] J.L. Ayala,et al. A banked precomputation-based CAM architecture for low-power storage-demanding applications , 2006, MELECON 2006 - 2006 IEEE Mediterranean Electrotechnical Conference.
[3] Joel Silberman,et al. Reducing power consumption during TLB lookups in a PowerPC/spl trade/ embedded processor , 2005, Sixth international symposium on quality electronic design (isqed'05).
[4] Cheng-Wen Wu,et al. A Low-Power CAM Design for LZ Data Compression , 2000, IEEE Trans. Computers.
[5] Mahmut T. Kandemir,et al. Leakage Current: Moore's Law Meets Static Power , 2003, Computer.
[6] Bin-Da Liu,et al. A low-power precomputation-based fully parallel content-addressable memory , 2003, IEEE J. Solid State Circuits.
[7] Ali Sheikholeslami,et al. A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories , 2003 .
[8] D. Blaauw,et al. Single-V/sub DD/ and single-V/sub T/ super-drowsy techniques for low-leakage high-performance instruction caches , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[9] Marisa López-Vallejo,et al. Leakage Energy Reduction in Banked Content Addressable Memories , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.
[10] K. Fujishima,et al. A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture , 2005, IEEE Journal of Solid-State Circuits.
[11] Huan Liu. Reducing routing table size using ternary-CAM , 2001, HOT 9 Interconnects. Symposium on High Performance Interconnects.
[12] T. Mudge,et al. Drowsy caches: simple techniques for reducing leakage power , 2002, Proceedings 29th Annual International Symposium on Computer Architecture.
[13] Yingtao Jiang,et al. CAM-based label search engine for MPLS over ATM networks , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).
[14] A. Sheikholeslami,et al. A current-saving match-line sensing scheme for content-addressable memories , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[15] K. Pagiamtzis,et al. Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..
[16] Hoi-Jun Yoo,et al. A 0.7-fJ/bit/search 2.2-ns search time hybrid-type TCAM architecture , 2004, IEEE Journal of Solid-State Circuits.