Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes

Detecting and correcting errors in logic circuits is much more difficult than in memories. While concurrent error detection and correction mechanisms can be efficiently incorporated in memories due to their regular structure, logic circuits present a much greater challenge because of their irregular structure. One approach to handle the problems arising due to soft errors is to detect the errors using a concurrent error detection (CED) circuitry that monitors the circuit output for the occurrence of an error. Once the error is detected the system can recover and hence prevent a failure. While operating in an environment with high soft error rate and for systems with a stringent reliability and availability requirement, error detection alone may not be sufficient. While triple modular redundancy (TMR) can mask all single faults, the overhead can be unacceptably high for the targeted applications. This paper presents a low-overhead non-intrusive technique to detect and correct the most likely soft errors using customized ad-hoc error detecting and correcting (EDAC) linear block codes. Employing the proposed EDAC scheme can dramatically reduce the failure rate and increase the mean time to failure (MTTF) for logic circuits with limited overhead. For certain types of applications e.g., network servers, query servers, etc., with high availability and low cost requirements, the proposed approach could be very useful. The linearity property of the codes allows for efficient synthesis of the parity prediction logic. The experimental results demonstrate the effectiveness of the proposed scheme.

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