Systolic architectures for radar CFAR detectors

Radar constant false alarm rate (CFAR) detectors, which are adaptive threshold detectors used to compensate for unknown noise environments, are discussed. Although the signal processing theory for CFAR detection is advanced, applications lag because of the high throughput required in radar. This intensive computational requirement (a data rate of at least 20 MHz for most search radars) cannot be met only by further advances in VLSI technology; parallel processing techniques are also needed. The feasibility of array processors based on VLSI technology enables the processing speed to increase by several orders of magnitude. One special-purpose VLSI architecture is the systolic array, which boasts massive concurrency. The concurrency in systolic arrays is derived from pipelined or parallel processing, and possibly both. Systolic array architectures are proposed for several important CFAR detectors.<<ETX>>