A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

This paper presents a time-interleaved pipelined-SAR ADC with on-chip offset cancellation technique. The design reuses the SAR ADC to perform offset cancellation, thus saving calibration costs. The inter-stage gain of 8 is implemented in a 6-bit capacitive DAC with a flip-around operation. A capacitive attenuation used in both the first and second DACs significantly reduces the power dissipation and optimizes conversion speed. The detailed circuit implementation of the subthreshold op-amp is discussed, and the possible limits caused by nonidealities are analyzed for a proper correction in the design. These include the inter-stage-gain error and various channel mismatches of offset, gain, and timing. Measurements of a 65-nm CMOS prototype operating at 160 MS/s and 1.1-V supply show an SNDR of 55.4 dB and 2.72 mW total power consumption.

[1]  Wenbo Liu,et al.  A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[2]  Chung-Ming Huang,et al.  A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[3]  Asad A. Abidi,et al.  A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[4]  Eric A. M. Klumperink,et al.  A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[5]  Jan Craninckx,et al.  A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS , 2009, IEEE Journal of Solid-State Circuits.

[6]  Franco Maloberti,et al.  A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[7]  Franco Maloberti,et al.  On-chip small capacitor mismatches measurement technique using beta-multiplier-biased ring oscillator , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[8]  Sai-Weng Sin,et al.  A threshold-embedded offset calibration technique for inverter-based flash ADCs , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[9]  Geert Van der Plas,et al.  A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  Franco Maloberti,et al.  A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[11]  Michael P. Flynn,et al.  A 12b 50MS/s 3.5mW SAR assisted 2-stage pipeline ADC , 2010, 2010 Symposium on VLSI Circuits.

[12]  Rui Paulo Martins,et al.  A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[13]  Franco Maloberti,et al.  An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H , 2010, 2010 Proceedings of ESSCIRC.

[14]  M. Furuta,et al.  A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques , 2007, IEEE Journal of Solid-State Circuits.

[15]  Sanroku Tsukamoto,et al.  Split capacitor DAC mismatch calibration in successive approximation ADC , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[16]  Sanroku Tsukamoto,et al.  A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[17]  K. Bacrania,et al.  A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse , 2007, IEEE Journal of Solid-State Circuits.

[18]  J. Jacob Wikner,et al.  CMOS Data Converters for Communications , 2000 .