High-speed low-power charge-buffered active-pull-down ECI circuit

A high-speed, low-power, charge-buffered active-pull-down ECL (emitter-coupled logic) circuit is described. The circuit features a charge-buffered coupling between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor. This coupling scheme provides a much larger dynamic current than what can be reasonably achieved through the capacitor coupling and a DC path to alleviate the AC-testing requirement. Furthermore, the dynamic current is utilized effectively by the logic stage, thus allowing a reduction in the power consumption of the logic stage without sacrificing the switching speed. Based on a 0.8- mu m double-poly self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 37% improvement in both the speed and load driving capability for a loaded gate compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed. >

[1]  M. Yamamoto,et al.  Advanced ECL with new active pull-down emitter-followers , 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.

[2]  T.H. Ning,et al.  Sub-300-ps CBL circuits , 1989, IEEE Electron Device Letters.

[3]  S. K. Wiedmann.  Charge Buffered Logic (CBL) - A New Complementary Bipolar Circuit Concept , 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers.

[4]  S.K. Wiedmann.  Potential of bipolar complementary device/Circuit technology , 1987, 1987 International Electron Devices Meeting.

[5]  Ching-Te Chuang.  NTL with complementary emitter-follower driver: a high-speed low-power push-pull logic circuit , 1990 .

[6]  Ching-Te Chuang,et al.  A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stage , 1989 .

[7]  Ching-Te Chuang,et al.  High-speed low-power charge-buffered active-pull-down ECL circuit , 1990, Proceedings on Bipolar Circuits and Technology Meeting.

[8]  J.D. Cressler,et al.  A submicrometer high-performance bipolar technology , 1989, IEEE Electron Device Letters.

[9]  Ching-Te Chuang,et al.  A 23 ps/2.1 mW ECL gate , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.