PWM Inverters Using Split-Wound Coupled Inductors

The number of output-voltage levels available in pulsewidth-modulated (PWM) voltage-source inverters can be increased by inserting a split-wound coupled inductor between the upper and lower switches in each inverter leg. Interleaved PWM control of both inverter-leg switches produces three-level PWM voltage waveforms at the center tap of the coupled inductor winding, representing the inverter-leg output terminal, with a PWM frequency twice the switching frequency. The winding leakage inductance is in series with the output terminal, with the main magnetizing inductance filtering the instantaneous PWM-cycle voltage differences between the upper and lower switches. Since PWM dead-time signal delays can be removed, higher device switching frequencies and higher fundamental output voltages are made possible. The proposed inverter topologies produce five-level PWM voltage waveforms between two inverter-leg terminals with a PWM frequency up to four times higher than the inverter switching frequency. This is achieved with half the number of switches used in alternative schemes. This paper uses simulated and experimental results to illustrate the operation of the proposed inverter structures.

[1]  Holmes,et al.  Pulse width modulation for power converters , 2003 .

[2]  Fang Zheng Peng,et al.  Dead-Time Elimination for Voltage Source Inverters , 2008, IEEE Transactions on Power Electronics.

[3]  Seung-Ki Sul,et al.  Inverter output voltage synthesis using novel dead time compensation , 1996 .

[4]  K. Smedley,et al.  Parallel operation of one-cycle controlled grid connected three-phase inverters , 2005, Fourtieth IAS Annual Meeting. Conference Record of the 2005 Industry Applications Conference, 2005..

[5]  Seung-Gi Jeong,et al.  The analysis and compensation of dead-time effects in PWM inverters , 1991 .

[6]  Tsai-Fu Wu,et al.  A single-stage fast regulator with PFC based on an asymmetrical half-bridge topology , 2005, IEEE Transactions on Industrial Electronics.

[7]  Keiju Matsui,et al.  Parallel-connections of pulsewidth modulated inverters using current sharing reactors , 1995 .

[8]  A. Knight,et al.  Coupled Three-Phase Inductors for Interleaved Inverter Switching , 2008, IEEE Transactions on Magnetics.

[9]  Fang Zheng Peng,et al.  Multilevel inverters: a survey of topologies, controls, and applications , 2002, IEEE Trans. Ind. Electron..

[10]  Thomas A. Lipo,et al.  On-line dead-time compensation technique for open-loop PWM-VSI drives , 1999 .

[11]  T.-P. Chen,et al.  Circulating zero-sequence current control of parallel three-phase inverters , 2006 .

[12]  Thomas A. Lipo,et al.  Dual AC-drive system with a reduced switch count , 2001 .

[13]  K. Matsui,et al.  A pulsewidth-modulated inverter with parallel connected transistors using current-sharing reactors , 1993 .

[14]  Yoshihiro Murai,et al.  Waveform Distortion and Correction Circuit for PWM Inverters with Switching Lag-Times , 1987, IEEE Transactions on Industry Applications.

[15]  J. Salmon,et al.  Single phase multi-level PWM Inverter topologies using coupled inductors , 2008, 2008 IEEE Power Electronics Specialists Conference.

[16]  Joo-Hyun Lee,et al.  A Dead Time Compensation Method in Voltage-Fed PWM Inverter , 2006, Conference Record of the 2006 IEEE Industry Applications Conference Forty-First IAS Annual Meeting.

[17]  Russel J. Kerkman,et al.  Current regulator instabilities on parallel voltage source inverters , 1997, IAS '97. Conference Record of the 1997 IEEE Industry Applications Conference Thirty-Second IAS Annual Meeting.

[18]  Longya Xu,et al.  Analysis of a Novel Stator Winding Structure Minimizing Harmonic Current and Torque Ripple for Dual Six-Step Converter-Fed High Power AC Machines , 1995, IEEE Transactions on Industry Applications.

[19]  Dushan Boroyevich,et al.  Control of circulating current in two parallel three-phase boost rectifiers , 2002 .

[20]  D. Casadei,et al.  Multilevel Operation of a Dual Two-Level Inverter with Power Balancing Capability , 2006, Conference Record of the 2006 IEEE Industry Applications Conference Forty-First IAS Annual Meeting.

[21]  Keiju Matsui,et al.  Application of parallel connected NPC-PWM inverters with multilevel modulation for AC motor drive , 2000 .

[22]  A.M. Khambadkone,et al.  Analysis and Implementation of a High Efficiency, Interleaved Current-Fed Full Bridge Converter for Fuel Cell System , 2007, IEEE Transactions on Power Electronics.

[23]  B. A. Welchko,et al.  Effects and Compensation of Dead-Time and Minimum Pulse-Width Limitations in Two-Level PWM Voltage Source Inverters , 2006, Conference Record of the 2006 IEEE Industry Applications Conference Forty-First IAS Annual Meeting.

[24]  Fred C. Lee,et al.  Interleaved PWM with discontinuous space-vector modulation , 1999 .

[25]  Jeffrey Ewanchuk,et al.  Performance of a High Speed Motor Drive System Using a Novel Multi-Level Inverter Topology , 2008, 2008 IEEE Industry Applications Society Annual Meeting.

[26]  P. N. Tekwani,et al.  A Reduced-Switch-Count Five-Level Inverter With Common-Mode Voltage Elimination for an Open-End Winding Induction Motor Drive , 2007, IEEE Transactions on Industrial Electronics.

[27]  C. Keller,et al.  Are paralleled IGBT modules or paralleled IGBT inverters the better choice , 2002 .

[28]  T. Martire,et al.  Optimization of the Supply Voltage System in Interleaved Converters Using Intercell Transformers , 2007, IEEE Transactions on Power Electronics.

[29]  Hyun-Soo Kim,et al.  On-line dead-time compensation method using disturbance observer , 2003 .