Temic 0.35 mum Technology and Sea of Gates for Space

We will report how we have hardened our 0.35 μm standard process for space, which we have installed in our 8” wafer fab in Rousset, France, and the resulting radiation test results with the MH1RT sea of gates test vehicle and a 1 Mbit SRAM demonstrating a capability in excess of 200 Krads for total dose, and 116 MeV/mg.cm2 for latch up. SEU hardened memory cells have been designed with the objective to raise the LET above 100 MeV/(mg.cm2). Introduction Advanced CMOS technologies of the 0.35μm generation and below are less sensitive to total dose radiation effects due to their reduced gate oxide thickness. Threshold voltage shift becomes tolerable as it is smaller than the manufacturing variation. But the parasitic n-channel device still shows a drift as a function of the total dose, its off-current increasing to an unacceptable value of 10 μA for doses of 100 Krads. The goal of this work was to increase the radiation tolerance of the standard CMOS technology to above 100 krads without the use of layout features which would increase device size. The second requirement is the elimination of latch up under heavy ion irradiation with energies up to 110 MeV/mg.cm2. And the last is to raise the SEU LET threshold of memory/DFF cells to an acceptable level, hopefully above 70 MeV. Eventually, we report the global characteristics of the MH1RT sea of gates series processed on this new technology. The technology hardening has been supported by CNES and the libraries development by ESTEC. 0.35μm CMOS characteristics The base line technology is a 4 layer metal CMOS process. It uses retrograde twin wells and epitaxial substrate. Source/drain and polysi gates are salicided. The interlevel and intermetal dielectric layers are planarized using Chemical Mechanical Polishing (CMP). Contacts and vias are filled with CMP planarized tungsten plugs. Minimum transistor gate length is 0.35μm. Metal1 pitch is 0.9μm, metal2, metal3 and metal 4 pitchs are 1.05μm. Process adaptation In order to suppress leakage current after irradiation in the parasitic n-channel device, which is formed between different NMOS transistors or NMOS transistor and n-well or which exists in parallel to the channel in the active NMOS transistor in the region of the transition between gate oxide and field oxide, the threshold voltage of this transistor can be raised. While this does not change the inherent sensitivity of the threshold voltage to irradiation, it gives sufficient margin to allow a negative shift of the threshold voltage, which remains higher than the maximum power supply voltage and therefor keeps this device in the off condition. The limiting factor of the threshold voltage raise, which is achieved by increasing the p-well doping, is the minimum junction breakdown voltage of the N+ source/drain junction. To reduce SEL sensitivity, the n-well doping is increased too. The epitaxial layer thickness was reduced to minimum value compatible with the existing twin well process. All these changes allow the mask compatibility of a product in the standard and radiation tolerant process.