Top-Down Design and Verification of Mixed-Signal Circuits

Provides and introduction and motivation for a top-down verification. Top-down verification is a refinement of the top-down design methodology that adds considerable rigor and greatly reduces the chance of a functional failure. The is paper was first presented in the 20 June 2005 issue of " The Planet Analog EE Times Magazine Supplement ". It was last updated on November 24, 2009. You can find the most recent version at www.designers-guide.com. Contact the authors via e-mail at consult-ing@designersguide.com. Permission to make copies, either paper or electronic, of this work for personal or classroom use is granted without fee provided that the copies are not made or distributed for profit or commercial advantage and that the copies are complete and unmodified. To distribute otherwise , to publish, to post on servers, or to distribute to lists, requires prior written permission. For more information on Analog Verification visit www.designers‐guide.com.