Kapees: A New Tool for Standard Cell Placement

We consider the well-known problem of efficient cell placement on a fixed die. We investigate minimization of half perimeter that is required for a design that in turn results into minimal routed wire length and thus wire delay. We describe a new method, Kapees, for large scale standard cell placement. Our technique is based on recursive partitioning of placement circuit which is modeled as a hypergraph. It uses partitioning during the global placement phase and a greedy approach is followed to reduce the wire length during detailed placement phase. Our results show a significant improvement in comparison to Cadence Encounter’s Amoeba and Capo tools by 9% and 5%, respectively.

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