A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology
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Yukihito Oowaki | Shigeyoshi Watanabe | Akihiro Nitayama | T. Kobayashi | Hiroshi Takato | Kazuya Ohuchi | A. Hojo | K. Numata | K. Tsuchiya | Kunio Tsuda | Naoko Takenouchi | Masahiko Chiba | A. Nitayama | H. Takato | Y. Oowaki | T. Kobayashi | K. Ohuchi | K. Tsuda | A. Hojo | M. Chiba | N. Takenouchi | S. Watanabe | K. Numata | K. Tsuchiya
[1] J. Lee,et al. A 8 × 8b parallel multiplier in submicron technology , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[2] Jun Iwamura,et al. A high speed and low power CMOS/SOS multiplier-accumulator , 1983 .
[3] M. Okabe,et al. An ECL 5000-gate gate array with 190-ps gate delay , 1986 .
[4] H. Ichino,et al. An 80ps 2500-gate bipolar macrocell array , 1985, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[5] K. Suganuma,et al. A CMOS/SOS multiplier , 1984, 1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[6] H. Ishikawa,et al. A GaAs 16×16b parallel multiplier using self alignment technology , 1983, 1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[7] Y. Kato,et al. A GaAs 8/spl times/8-bit multiplier/accumulator using JFET DCFL , 1986 .
[8] Christopher S. Wallace,et al. A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..
[9] J. Greene,et al. A CMOS 32b Wallace tree multiplier-accumulator , 1986, 1986 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[10] M. Suzuki,et al. Prospects of SST technology for high speed LSI , 1985, 1985 International Electron Devices Meeting.