SoC — A real challenge for ESD protection?

We are facing the task to provide ESD protection concepts for complex system on chip (SoC) solutions including RF components, high voltage circuits and mixed signal functionality. Critical issues like protection of sensitive interfaces between supply domains, ESD master bus, system level ESD/EOS requirements and test methodology, are reviewed. Concepts are presented for a SoC and a system-in-package product in a 0.13 mum CMOS process.

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