A Simulation Study on the Performance Improvement of CMOS Devices Using Alternative Gate Electrode Structures

The success of the microelectronics industry over more then 30 years is to a large extent based on unimaginable device scaling governed by the Moore’s law, which also resulted in performance improvements. The advances were mainly possible due to the unique properties of SiO2, which is grown by thermal oxidation and poly silicon gate technologies which substituted aluminum metal gates and enabled the self aligned gate technologies. However, the aggressive scaling of Complementary Metal Oxide Semiconductor (CMOS) devices is driving SiO2 based gate dielectrics to its physical limits as stated in the International Technology Roadmap for Semiconductors (ITRS). The scaling of device dimensions, especially the gate oxide thickness its physical limits required novel gate stack technologies, in which replacement of conventional SiO2 with a high-K material is one of them. The usage of high-K gate materials enables the scaling of the equivalent oxide thickness (EOT) of gate dielectric into sub 1 nm regime while allowing much higher physical thickness. The feasibility of scaling EOT down to sub 1 nm results in degraded performance due to the gate oxide and non-ideal gate electrode. This work mainly discusses the performance issues of the CMOS devices and possible ways to make improvements. When considering the biasing conditions of a CMOS device, the n+-poly gate of a n-channel Metal Oxide Semiconductor Field Effect Transistor (NMOSFET) is biased with a positive voltage and the p+-poly gate of a p-channel Metal Oxide Semiconductor Field Effect Transistor (PMOSFET) is biased with a negative voltage. As a result of the biasing condition, a depletion layer is formed at the gate electrode-gate oxide interface. This gate depletion is called poly gate depletion effect, results in a capacitance in series with the gate oxide capacitance. This poly gate depletion capacitance results in a decreased gate capacitance and thus results in degraded device performance. In thick oxide systems, where the gate oxide is around more than 10 nm, the gate depletion effects can be neglected as the contribution from poly gate depletion capacitance is small when compared to the gate oxide capacitance. In thin oxide systems, where the oxide thickness is less than 4 nm, the poly gate depletion effect cannot be neglected. However, degenerately doped gate electrodes can be used to suppress the poly gate depletion capacitance, by decreasing the thickness of the depletion layer formed at the gate electrode-gate oxide interface. These highly doped gate electrodes combined with thin gate oxides allow the dopants to distribute through the gate oxide and thus change the dopant distribution profile in both the gate electrode and the substrate. In ultra thin oxide systems, where the EOT is less than 2 nm, the poly gate deletion effects are unavoidable despite the gate being very highly doped. The depleted poly gate consists of parasitic charges because the ionized dopants and the parasitic charge density increases with increased doping. These parasitic gate charges act as charge centers in the gate and scatter the carries in the channel thus degrading the device performance, an effect called remote Coulomb scattering. In order to decrease the effect of remote Coulomb scattering, the parasitic gate charge density should be decreased, by reducing gate doping concentration. The reduced gate doping results in increase poly gate depletion and degrade the device performance. Thus, it is clear that the effects poly gate depletion and/or remote Coulomb scattering are unavoidable in conventionally doped gate CMOS devices. To reduce poly gate depletion and remote Coulomb scattering, the gate depletion should be completely eliminated. Metal gates provide a possible solution to eliminate poly gate depletion completely but the integration of metal gates is difficult. In order to reduce the poly gate depletion effects, an alternative gate doping scheme, where the gate is inversely doped is proposed in this work. With inversely doped gates the poly gate depletion is eliminated selectively when the device is turned on. The gate in conventional CMOS devices is generally of the same type as that of the source/drain, i.e., the NMOSFET has a n-gate and the PMOSFET has a p-gate. In an alternative gate doping scheme, the n-gate of the NMOSFET is replaced with a p-gate and vice versa for a PMOSFET. As a result, the gate is driven into accumulation when the device is turned on, thus retaining the gate capacitance at its maximum possible value of oxide capacitance. As the gate capacitance is retained at its maximum value, the device performance improves. The concept of alternative gate doping was verified by fabricating suitable hardware. Through extensive simulation studies, the concept of alternate gate doping was investigated in detail. Further simulations suggested that the concept can even be implemented in silicon on insulator devices. The simulation results suggested that the device performance can be improved significantly, thus allowing the use of poly gates even in sub 100nm regime.