A 20Gb/s digitally adaptive equalizer/DFE with blind sampling

As data rates increase, the backplane communication systems suffer from serious inter-symbol interference (ISI). Due to different channel lengths, loss, and environment variations, an adaptive equalizer is an attractive and robust circuit to equalize the received data in high-speed data communications. Several tech-niaques are presented for adaptive equalizers. In [1], a spectrum balancing method is presented for an analog equalizer. However, this method is valid only for the random data with fixed data rate. In [5], an eye-opening-monitor (EOM) method adopts a two-dimensional map to detect the signal quality. This EOM method needs a synchronous sampling clock and high-speed comparators. It results in high power consumption and furthermore it requires accurate analog circuits.

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[2]  Daniel Friedman,et al.  A 19Gb/s 38mW 1-tap speculative DFE receiver in 90nm CMOS , 2009, 2009 Symposium on VLSI Circuits.

[3]  Sung Min Park,et al.  10 gbit/s 0.0065 mm 2 6 mw analogue adaptive equaliser utilising negative capacitance , 2009 .

[4]  Jri Lee.  A 20-Gb/s Adaptive Equalizer in 0.13-$muhbox m$CMOS Technology , 2006, IEEE Journal of Solid-State Circuits.

[5]  Hiroaki Uchida,et al.  A 40Gb/s CDR with Adaptive Decision-Point Control Using Eye-Opening-Monitor Feedback , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[6]  Jri Lee,et al.  A 21-Gb/s 87-mW transceiver with FFE/DFE/linear equalizer in 65-nm CMOS technology , 2009, 2009 Symposium on VLSI Circuits.