A Neuron-MOS Neural Network Using Low-Power Self-Learning-Compatible Synapse Cells

A self-learning neural network hardware has been developed using Neuron MOS Transistor (vMOS) as a key circuit element, which is a functional device simulating the actions of biological neurons at a single transistor level [1]. Synapse cells are formed by merging an EEPROM memory cell into a new-concept vMOS differential-source-follower circuitry. As a result, synaptic connections free from standby power dissipation and featuring excellent weight-updating characteristics have been established. The operation of the synapse cells and vMOS neural networks has been verified using test circuits fabricated by a double-polysilicon CMOS process. An interesting feature of the synapse cell, the acceleration effect in learning, is also presented. s-rv-3