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[1] Gabriel H. Loh,et al. 3D-Stacked Memory Architectures for Multi-core Processors , 2008, 2008 International Symposium on Computer Architecture.
[2] Nikil D. Dutt,et al. RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor , 2010, HiPEAC.
[3] José Manuel Moya,et al. Leakage and temperature aware server control for improving energy efficiency in data centers , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[4] Yang Zhang,et al. Corey: An Operating System for Many Cores , 2008, OSDI.
[5] Jung Ho Ahn,et al. McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[6] Tajana Simunic,et al. CoMETC: Coordinated management of energy/thermal/cooling in servers , 2013, ACM Trans. Design Autom. Electr. Syst..
[7] Lizy Kurian John,et al. Analysis of dynamic power management on multi-core processors , 2008, ICS '08.
[8] Houman Homayoun,et al. Heterogeneous HMC+DDRx Memory Management , 2017 .
[9] Seung-Moon Yoo,et al. A framework for dynamic energy efficiency and temperature management , 2000, Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000.
[10] Lei Zhou,et al. DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[11] Hamid Sarbazi-Azad,et al. ITAP: Idle-Time-Aware Power Management for GPU Execution Units , 2019, ACM Trans. Archit. Code Optim..
[12] Yuan Xie,et al. Processor Design in 3D Die-Stacking Technologies , 2007, IEEE Micro.
[13] Muhammad Shafique,et al. Power and thermal management in massive multicore chips: Theoretical foundation meets architectural innovation and resource allocation , 2016, 2016 International Conference on Compliers, Architectures, and Sythesis of Embedded Systems (CASES).
[14] David M. Brooks,et al. Dimetrodon: Processor-level preventive thermal management via idle cycle injection , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).
[15] Larry Rudolph,et al. Metrics and Benchmarking for Parallel Job Scheduling , 1998, JSSPP.
[16] Bruce Jacob,et al. DRAMsim3: A Cycle-Accurate, Thermal-Capable DRAM Simulator , 2020, IEEE Computer Architecture Letters.
[17] Petru Eles,et al. On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration , 2009, 2009 46th ACM/IEEE Design Automation Conference.
[18] Yuan Xie,et al. Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).
[19] Kun Cao,et al. A survey of optimization techniques for thermal-aware 3D processors , 2019, J. Syst. Archit..
[20] Robin Wilson,et al. Temperature- and Voltage-Aware Timing Analysis , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[21] Jaeha Kung,et al. High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory , 2021, ACM Trans. Design Autom. Electr. Syst..
[22] Heba Khdr,et al. New trends in dark silicon , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[23] Sherief Reda,et al. Thermal prediction and adaptive control through workload phase detection , 2013, TODE.
[24] Heba Khdr,et al. mDTM: Multi-objective dynamic thermal management for on-chip systems , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[25] Amir Zjajo,et al. Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[26] Reza Salkhordeh,et al. An Operating System level data migration scheme in hybrid DRAM-NVM memory architecture , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[27] Enrico Macii,et al. Thermal-Aware Design Techniques for Nanometer CMOS Circuits , 2008, J. Low Power Electron..
[28] Sudhakar Yalamanchili,et al. Near Data Processing: Impact and Optimization of 3D Memory System Architecture on the Uncore , 2015, MEMSYS.
[29] Marco D. Santambrogio,et al. ThermOS: System support for dynamic thermal management of chip multi-processors , 2013, Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques.
[30] Heba Khdr,et al. SmartBoost: Lightweight ML-Driven Boosting for Thermally-Constrained Many-Core Processors , 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).
[31] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[32] Ankur Srivastava,et al. HMCTherm: a cycle-accurate HMC simulator integrated with detailed power and thermal simulation , 2018, MEMSYS.
[33] Muhammad Shafique,et al. Improving mobile gaming performance through cooperative CPU-GPU thermal management , 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).
[34] Amit Kumar Singh,et al. LifeSim: A lifetime reliability simulator for manycore systems , 2018, 2018 IEEE 8th Annual Computing and Communication Workshop and Conference (CCWC).
[35] Sheldon X.-D. Tan,et al. A Fast Leakage-Aware Full-Chip Transient Thermal Estimation Method , 2018, IEEE Transactions on Computers.
[36] Jóakim von Kistowski,et al. SPEC CPU2017: Next-Generation Compute Benchmark , 2018, ICPE Companion.
[37] Kevin Skadron,et al. HotSpot 6.0: Validation, Acceleration and Extension , 2015 .
[38] TingTing Hwang,et al. Thermal-aware dynamic page allocation policy by future access patterns for Hybrid Memory Cube (HMC) , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[39] Smruti R. Sarangi,et al. A Fast Leakage-Aware Green’s-Function-Based Thermal Simulator for 3-D Chips , 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[40] Jung Ho Ahn,et al. CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[41] Jörg Henkel,et al. HotSniper: Sniper-Based Toolchain for Many-Core Thermal Simulations in Open Systems , 2019, IEEE Embedded Systems Letters.
[42] Siddharth Garg,et al. Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors , 2014, TODE.
[43] Wei Zhang,et al. Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip , 2018, IEEE Transactions on Computers.
[44] Michael C. Huang,et al. A framework for dynamic energy efficiency and temperature management , 2000, MICRO 33.
[45] Wei Liu,et al. Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[46] Bruce Jacob,et al. The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It , 2009, The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It.
[47] David Atienza,et al. 3D-ICE: A Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs , 2014, IEEE Transactions on Computers.
[48] Stijn Eyerman,et al. An Evaluation of High-Level Mechanistic Core Models , 2014, ACM Trans. Archit. Code Optim..
[49] Amit Kumar Singh,et al. Thermal-aware mapping of streaming applications on 3D Multi-Processor Systems , 2013, The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia.
[50] Smruti R. Sarangi,et al. Variability-Aware Thermal Simulation using CNNs , 2021, 2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID).
[51] Preeti Ranjan Panda,et al. Leakage-Aware Dynamic Thermal Management of 3D Memories , 2020, ACM Trans. Design Autom. Electr. Syst..
[52] Pascal Vivet,et al. Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits , 2016, IEEE Design & Test.
[53] Avinash Sodani,et al. Knights landing (KNL): 2nd Generation Intel® Xeon Phi processor , 2015, 2015 IEEE Hot Chips 27 Symposium (HCS).
[54] David Atienza,et al. Neural network based on-chip thermal simulator , 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.
[55] Anoop Gupta,et al. The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.