Co-Simulation of Hybrid SDL and VHDL Specifications

The co-simulation is the chosen method within the ESPRIT Project INSYDE for the validation of hybrid SDL and VHDL specifications. This paper presents a concept for the integrated SDL and VHDL simulator and its realization in C++. The INSYDE concept for the co-simulation is based on the connection of two existing commercial simulators by the Coupling Module. The Integrated Simulator presented in this document aims at studying the functionality of this Coupling Module and the general principles of co-simulation.