Equivalence Checking of Finite State Machines with SMV

In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model M = M × M from two FSMs M and M. And we also get the temporal logic formula Φ from the equivalence checking definition. Then, we can check with model checker whether if satisfies Φ, written M Φ. Two FSMs are equivalent, if MΦ. Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.