Design and Simulation of High Speed 8-bit Vedic Multiplier Using Barrel Shifter on FPGA

Vedic mathematics[1] is an ancient technique with unique approach and it has got different sutras. Here, in this paper „Nikhilam Navatascaramam Dasatah‟ Sutra is been discussed , which is efficient in speed of the multiplier.This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multipliers. In our design we have utilized 8-bit barrel shifter which requires only one clock cycle for „n‟ number of shifts. The design is implemented and verified using FPGA and ISE Simulator.The propagation delay comparison was extracted from the synthesis report and static timing report as well. The design could achieve propagation delay of 5.323ns which is significantly less than conventional multipliers. Keywords– vedic mathematics,multiplier,barrel shifter,delay,fpga