Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing

This paper presents an area-efficient algorithm for the pipelined processing of fast Fourier transform (FFT). The proposed algorithm is to decompose a discrete Fourier transform (DFT) into two balanced sub-DFTs in order to minimize the total number of twiddle factors to be stored into tables. The radix in the proposed decomposition is adaptively changed according to the remaining transform length to make the transform lengths of sub-DFTs resulting from the decomposition as close as possible. An 8192-point pipelined FFT processor designed for digital video broadcasting-terrestrial (DVB-T) systems saves 33% of general multipliers and 23% of the total size of twiddle factor tables compared to a conventional pipelined FFT processor based on the radix-22 algorithm. In addition to the decomposition, several implementation techniques are proposed to reduce area, such as a simple index generator of twiddle factor and add/subtract units combined with the two's complement operation

[1]  Hong Ren Wu,et al.  The structure of vector radix fast Fourier transforms , 1989, IEEE Trans. Acoust. Speech Signal Process..

[2]  Viktor Öwall,et al.  A 2048 complex point FFT processor using a novel data scaling approach , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[3]  C. Joanblanq,et al.  A fast single-chip implementation of 8192 complex point FFT , 1995 .

[4]  Kyung-Wook Shin,et al.  A VLSI array processor for 16-point FFT , 1991 .

[5]  Harold S. Stone,et al.  Parallel Processing with the Perfect Shuffle , 1971, IEEE Transactions on Computers.

[6]  Shousheng He,et al.  Designing pipeline FFT processor for OFDM (de)modulation , 1998, 1998 URSI International Symposium on Signals, Systems, and Electronics. Conference Proceedings (Cat. No.98EX167).

[7]  Hannu Tenhunen,et al.  A new VLSI-oriented FFT algorithm and implementation , 1998, Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372).

[8]  P. Duhamel,et al.  `Split radix' FFT algorithm , 1984 .

[9]  Yunho Jung,et al.  New efficient FFT algorithm and pipeline implementation results for OFDM/DMT applications , 2003, IEEE Trans. Consumer Electron..

[10]  Alvin M. Despain,et al.  Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations , 1984, IEEE Transactions on Computers.

[11]  J. Tukey,et al.  An algorithm for the machine calculation of complex Fourier series , 1965 .

[12]  C. K. Yuen,et al.  Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.

[13]  E.E. Swartzlander,et al.  A radix 4 delay commutator for fast Fourier transform processor implementation , 1984, IEEE Journal of Solid-State Circuits.

[14]  D. Takahashi,et al.  An extended split-radix FFT algorithm , 2001, IEEE Signal Processing Letters.

[15]  Shousheng He,et al.  Design and implementation of a 1024-point pipeline FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[16]  Alvin M. Despain,et al.  Fourier Transform Computers Using CORDIC Iterations , 1974, IEEE Transactions on Computers.

[17]  Chi-Ying Tsui,et al.  IEEE Transactions on Circuits and Systems—I:Regular Papers information for authors , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  V. Boriakoff,et al.  FFT computation with systolic arrays, a new architecture , 1994 .

[19]  I. J. Good,et al.  The Relationship Between Two Fast Fourier Transforms , 1971, IEEE Transactions on Computers.

[20]  Yu-Wei Lin,et al.  A dynamic scaling FFT processor for DVB-T applications , 2004, IEEE Journal of Solid-State Circuits.

[21]  Robert Michael Owens,et al.  An architecture for a VLSI FFT processor , 1983, Integr..

[22]  Bevan M. Baas,et al.  A low-power, high-performance, 1024-point FFT processor , 1999, IEEE J. Solid State Circuits.

[23]  Framing structure , channel coding and modulation for digital terrestrial television , 2022 .

[24]  Vinod Subramaniam,et al.  Digital video broadcasting (DVB); framing structure, channel coding and modulation for digital terr , 2001 .