A novel strain enhanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films

A novel CMOS architecture utilizing tensile/compressive silicon nitride capping layers to induce tensile/compressive strain in NMOSFET/PMOSFET channel regions was developed. NMOSFET device delivers 1.05mA//spl mu/m on-current for 70nA//spl mu/m off-current at IV drain voltage. PMOS device exhibits peak 66% increase of linear drain current and 55% increase of saturation current. It was shown that drain current improvements both for N- and PMOSFETs strongly correlate with channel doping levels. Therefore, advanced methods of shallow and low resistance junction formation are required for maintaining low channel doping concentration and efficiently utilizing channel strain at sub-40nm gate length.