THE MIXED-VOLTAGE PROCESS

A new latch-up failure phenomenon induced by the parasitic P-N-P-N path between different power pins is reported here. This latch-np failure is observed in 0.13um and 0.18um process, but the test passes in 0.25um. A traditional latch-up prevention methodology of guide-ring insertion works well here, and the chip designers need to be aware of this phenomenon before the chip is tape-out.

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