Multi-bit pipeline analog-to-digital converter having amplifier sharing structure

The invention of the multi-amplifier sharing structure - SHA that removes a sampling error of that, by sampling and holding the input analog voltage, the input voltage of the converter digital-bit pipelined analog; First to K (K≥2 integer) N (N≥1 integer) of the stages and outputting the received input analog signal into a digital signal-bit flash ADC (Analog-to-Digital Converter); The first to N- bit MDAC (Multiplying Digital-to-Analog Converter) of the K-stage conversion outputs a difference between the output signal of the digital signal and the preceding stage outputted from the N- bit flash ADC back into an analog signal; In the first clock it is characterized in that connected to the output of the N- bit MDAC of the first stage and includes a three-stage amplifier coupled to the output of the SHA at the second clock. According to the invention, a multi-is that power consumption is share many SHA and the amplifier between the MDAC of the first stage in the bit pipeline ADC possible, thereby minimizing the power consumption and the effect of reducing the chip area is. Pipeline analog-to-digital converter, ADC, the amplifier, shared, SHA, MDAC