Efficient error detection and correction method for 1-out-of-3 binary signed digit adders

ABSTRACT Binary Signed Digit (BSD) number system has been extensively used in high-speed applications due to taking carry-free adders and high-speed multipliers. The 1-out-of-3 BSD encoding is an inherently fault-tolerant BSD encoding, which is a subset of m-out-of-n codes widely employed for error detection and correction. Although some fault-tolerant methods have been already proposed for 1-out-of-3 BSD adder, an efficient structure with both capabilities of fault detection and correction has not been introduced yet. In this paper, a 1-out-of-3 BSD adder with error detection and correction capabilities is presented. In spite of the negligible penalties in delay, power consumption, and area overhead, synthesis results show that more fault tolerance capability is achieved by the proposed method.

[1]  Marco Ottavi,et al.  Fault localization, error correction, and graceful degradation in radix 2 signed digit-based adders , 2006, IEEE Transactions on Computers.

[2]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[3]  Rakshith Saligram,et al.  Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates , 2013 .

[4]  Marco Ottavi,et al.  Error detection in signed digit arithmetic circuit with parity checker [adder example] , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[5]  Ghulam M. Chaudhry,et al.  Binary signed digit adder design with error detection capability , 2007, 2007 9th International Symposium on Signal Processing and Its Applications.

[6]  Jacob A. Abraham,et al.  On-line error detecting constant delay adder , 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

[7]  Behrooz Parhami,et al.  Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations , 1990, IEEE Trans. Computers.

[8]  Omid Kavehei,et al.  Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[9]  Mahmood Fazlali,et al.  A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation , 2010, 2010 IEEE International Conference on Computer Design.

[10]  Somayeh Timarchi,et al.  Low power design of binary signed digit residue number system adder , 2016, 2016 24th Iranian Conference on Electrical Engineering (ICEE).

[11]  A. Singh,et al.  Fault-tolerant systems , 1990, Computer.

[12]  Somayeh Timarchi,et al.  Efficient 1-out-of-3 Binary Signed-Digit multiplier for the moduli set {2n-1, 2n, 2n+1} , 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

[13]  Somayeh Timarchi,et al.  Optimized Parity-Based Error Detection and Correction Methods for Residue Number System , 2019, J. Circuits Syst. Comput..

[14]  Israel Koren,et al.  Fault-Tolerant Systems , 2007 .

[15]  Mahmood Fazlali,et al.  High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding , 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

[16]  N. R. Alamelu,et al.  SELF CHECKING AND FAULT TOLERANT DIGITAL DESIGN , 2009 .

[17]  Mahmood Fazlali,et al.  Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n - 1, 2n, 2n + 1} , 2012, IET Comput. Digit. Tech..

[18]  Constantin Halatsis,et al.  An Efficient TSC 1-out-of-3 Code Checker , 1990, IEEE Trans. Computers.