Realizing a Planar 4H-SiC Junctionless FET for Sub-10-nm Regime Using P+ Pocket

In this paper, using calibrated device simulations, we propose the use of a P⁺ pocket at channel–drain and channel–source interfaces in 4H-SiC junctionless FET (4H-SiC p-JLFET) to achieve efficient volume depletion in the sub-10-nm regime; thus relaxing the need of channel thickness scaling or the use of complex device architectures. The P⁺ pocket improves the OFF-state current (I_OFF) by ~ 10⁹, while slightly degrading the ON-state current (I_ON) and subthreshold slope (SS) for a 7-nm channel length device. This large gain in I_OFF presents the possibility of realizing multiple threshold voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula>) devices by tuning the metal-gate work function, which helps in creating optimized designs in terms of area, power, leakage, and performance, which is not possible in Si JLFETs, due to their need of high metal-gate work functions to achieve volume depletion even at larger channel lengths. The 4H-SiC p-JLFET gives ~1pA/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}~\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ </tex-math></inline-formula> even at an elevated temperature of 600 K. We also discuss the scaling of the SiC p-JLFETs for 7- and 5-nm channel length.