Cell-Aware Test

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.

[1]  Camelia Hora,et al.  Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality , 2008, 2008 IEEE International Test Conference.

[2]  Jochen A. G. Jess,et al.  On accurate modeling and efficient simulation of CMOS opens , 1993, Proceedings of IEEE International Test Conference - (ITC).

[3]  Mark Mohammad Tehranipoor,et al.  Circuit Topology-Based Test Pattern Generation for Small-Delay Defects , 2010, 2010 19th IEEE Asian Test Symposium.

[4]  K. C. Y. Mei,et al.  Bridging and Stuck-At Faults , 1974, IEEE Transactions on Computers.

[5]  Daniel G. Saab,et al.  CRIS: a test cultivation program for sequential VLSI circuits , 1992, ICCAD.

[6]  Wojciech Maly,et al.  Fault characterization of standard cell libraries using inductive contamination analysis (ICA) , 1996, Proceedings of 14th VLSI Test Symposium.

[7]  Mario J. Paniccia,et al.  Laser voltage probe (LVP): a novel optical probing technology for flip-chip packaged microprocessors , 1999, Proceedings of the 1999 7th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.99TH8394).

[8]  Edward J. McCluskey,et al.  Gate exhaustive testing , 2005, IEEE International Conference on Test, 2005..

[9]  Robert C. Aitken.  Finding defects with fault models , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[10]  Tracy Larrabee,et al.  Test Pattern Generation for Realistic Bridge Faults in CMOS ICs , 1991, 1991, Proceedings. International Test Conference.

[11]  Janusz Rajski,et al.  Stuck-open and transition fault testing in CMOS complex gates , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[12]  Martin Keim.  Improving Failure Analysis for Cell-Internal Defects through Cell Aware Technology , 2013 .

[13]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[14]  Friedrich Hapke,et al.  Cell-aware analysis for small-delay effects and production test results from different fault models , 2011, 2011 IEEE International Test Conference.

[15]  Friedrich Hapke,et al.  Defect-oriented cell-internal testing , 2010, 2010 IEEE International Test Conference.

[16]  Federal Reserve Board and Federal Reserve Bank of San Francisco, res p e c t ive ly. The authors would like to thank , 2022 .

[17]  Friedrich Hapke,et al.  Embedded multi-detect ATPG and Its Effect on the Detection of Unmodeled Defects , 2007, 2007 IEEE International Test Conference.

[18]  Albrecht P. Stroele,et al.  A unified approach to the extraction of realistic multiple bridging and break faults , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[19]  Friedrich Hapke,et al.  Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates , 2012, 2012 17th IEEE European Test Symposium (ETS).

[20]  Irith Pomeranz,et al.  On n-detection test sets and variable n-detection test sets for transition faults , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[21]  D. Faure,et al.  Electrical characterization by sub-micron probing technique on 90 nm CMOS technology for failure analysis , 2004, Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2004 (IEEE Cat. No.04TH8743).

[22]  Peter Lidén,et al.  A fault model for switch-level simulation of gate-to-drain shorts , 1996, Proceedings of 14th VLSI Test Symposium.

[23]  Friedrich Hapke,et al.  Gate-Exhaustive and Cell-Aware pattern sets for industrial designs , 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

[24]  Bernd Becker,et al.  Resistive Bridging Fault Simulation of Industrial Circuits , 2008, 2008 Design, Automation and Test in Europe.

[25]  Friedrich Hapke,et al.  Cell-aware Production test results from a 32-nm notebook processor , 2012, 2012 IEEE International Test Conference.

[26]  Janak H. Patel,et al.  Fast and accurate CMOS bridging fault simulation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[27]  Camelia Hora,et al.  Defect-oriented cell-aware ATPG and fault simulation for industrial cell libraries and designs , 2009, 2009 International Test Conference.

[28]  Robert Puers,et al.  A review of focused ion beam applications in microsystem technology , 2001 .

[29]  Chen Wang,et al.  Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects , 2006, 2006 15th Asian Test Symposium.

[30]  J. Rajski,et al.  Cell-aware Production Test Results from a 350 nm Automotive Design , 2013 .

[31]  Stephen J. Pennycook,et al.  Scanning transmission electron microscopy : imaging and analysis , 2011 .

[32]  John Paul Shen,et al.  Extraction and simulation of realistic CMOS faults using inductive fault analysis , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[33]  Sudhakar M. Reddy,et al.  Transistor Level Test Generation for MOS Circuits , 1985, 22nd ACM/IEEE Design Automation Conference.