论文信息 - A novel high-performance low-power CMOS master-slave flip-flop

A novel high-performance low-power CMOS master-slave flip-flop

A novel high-performance low-power CMOS master-slave flip-flop is proposed. The proposed flip-flop consumes very low power, while having a very small clock load and data load. In our HSPICE simulations, the new flip-flop has an optimal power-delay product better than previous master-slave structures. The proposed flip-flop is compared to other reported master-slave flip-flops.

Shih-Lien Lu | S. Hsu

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