Hardware-Based Performance Enhancement Guaranteed Caches

Cache memories are widely used in microprocessors to improve the average-case memory performance. However, they are harmful to time predictability, and thus may not be desirable for real-time systems. In this paper, we make simple hardware extensions of a regular cache to implement the performance enhancement guaranteed cache (PEG-C). The PEG-C is totally controlled by hardware, which can automatically improve the average-case performance of real-time software with guaranteed and enhanced worst-case performance.

[1]  Isabelle Puaut,et al.  Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison , 2007 .

[2]  Ting Chen,et al.  WCET centric data allocation to scratchpad memory , 2005, 26th IEEE International Real-Time Systems Symposium (RTSS'05).

[3]  Yun Liang,et al.  WCET-centric partial instruction cache locking , 2012, DAC Design Automation Conference 2012.

[4]  Francisco J. Cazorla,et al.  Hardware support for WCET analysis of hard real-time multicore systems , 2009, ISCA '09.

[5]  Martin Schoeberl,et al.  Time-Predictable Computer Architecture , 2009, EURASIP J. Embed. Syst..

[6]  Isabelle Puaut,et al.  WCET-centric software-controlled instruction caches for hard real-time systems , 2006, 18th Euromicro Conference on Real-Time Systems (ECRTS'06).

[7]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[8]  P. Cochat,et al.  Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.

[9]  Martin Schoeberl,et al.  A Time Predictable Instruction Cache for a Java Processor , 2004, OTM Workshops.

[10]  Frank Müller,et al.  Generalizing timing predictions to set-associative caches , 1997, Proceedings Ninth Euromicro Workshop on Real Time Systems.

[11]  Yudong Tan,et al.  A Prioritized Cache for Multi- tasking Real-time Systems , 2004 .

[12]  David B. Whalley,et al.  Bounding worst-case instruction cache performance , 1994, 1994 Proceedings Real-Time Systems Symposium.

[13]  Jason Cong,et al.  An energy-efficient adaptive hybrid cache , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[14]  Jane W.-S. Liu Real-Time Systems , 2000, Encyclopedia of Algorithms.

[15]  Reinhard Wilhelm,et al.  The influence of processor architecture on the design and the results of WCET tools , 2003, Proceedings of the IEEE.

[16]  Jean-François Deverge,et al.  WCET-Directed Dynamic Scratchpad Memory Allocation of Data , 2007, 19th Euromicro Conference on Real-Time Systems (ECRTS'07).

[17]  Reinhard Wilhelm,et al.  Cache Behavior Prediction by Abstract Interpretation , 1996, Sci. Comput. Program..

[18]  Hui Wu,et al.  Optimal WCET-aware code selection for scratchpad memory , 2010, EMSOFT '10.

[19]  Tulika Mitra,et al.  Exploring locking & partitioning for predictable shared caches on multi-cores , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[20]  Per Stenström,et al.  Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[21]  Bruce Jacob,et al.  Cache Design for Embedded Real-Time Systems , 1999 .

[22]  Miodrag Potkonjak,et al.  MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.

[23]  Anant Agarwal,et al.  Software-based instruction caching for embedded processors , 2006, ASPLOS XII.

[24]  Jakob Engblom,et al.  Requirements for and Design of a Processor with Predictable Timing , 2004, Design of Systems with Predictable Behaviour.

[25]  Peter Marwedel,et al.  Scratchpad memory: a design alternative for cache on-chip memory in embedded systems , 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

[26]  Filip Sebek Determining the Worst-Case Instruction Cache Miss-Ratio , 2002 .

[27]  Björn Lisper,et al.  Data cache locking for higher program predictability , 2003, SIGMETRICS '03.

[28]  Srinivas Devadas,et al.  Dynamic Cache Partitioning via Columnization , 2000, DAC 2000.

[29]  Wei Zhang,et al.  Hybrid SPM-cache architectures to achieve high time predictability and performance , 2013, 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors.

[30]  P. Marwedel,et al.  Influence of Onchip Scratchpad Memories on WCET prediction ∗ , 2004 .

[31]  D. B. Kirk,et al.  SMART (strategic memory allocation for real-time) cache design , 1989, [1989] Proceedings. Real-Time Systems Symposium.

[32]  Alexander G. Dean,et al.  Leveraging both Data Cache and Scratchpad Memory through Synergetic Data Allocation , 2012, 2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium.

[33]  Robert Richmond,et al.  The Book of Overclocking: Tweak Your PC to Unleash Its Power , 2003 .

[34]  Sharad Malik,et al.  Performance analysis of embedded software using implicit path enumeration , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[35]  Damien Hardy,et al.  WCET analysis of multi-level set-associative instruction caches , 2008, ArXiv.

[36]  Jaehyuk Huh,et al.  Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture , 2003, IEEE Micro.

[37]  Abhik Roychoudhury,et al.  Scope-Aware Data Cache Analysis for WCET Estimation , 2011, 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium.

[38]  Wei Zhang,et al.  PEG-C: Performance Enhancement Guaranteed Cache for Hard Real-Time Systems , 2014, IEEE Embedded Systems Letters.