Themaintaskoftheinterlock system istoprevent anydamagetothecostexpensive components oftheRF station. The implementation oftheinterlock shouldguarantee a maximumofuninterrupted timeofoperation whichincludes the implementation ofself diagnostic andrepair strategies onmodule basis. Additional tasks include collection andtemporary storage ofstatus information ofindividual channels; transfer ofthis information toa higherlevel control system, butalsothe enactment ofslowcontrol functions. Theinterlock implementation isbasedona 4U 19"-Crate whichhousesa controller anddifferent slavemoduleswhich implement theinterface tothecomponents oftheRF station. A dedicated, userdefined backplane connects thecontroller toall slave modules. TheController incorporates a32-bit RISCNIOS-II processor inside a Cyclone-It FPGA device fromALTERA 161. The programrunningon thisprocessor performs allnecessary control andmonitoring functions toallslavemodulesinthe crate, butnottheinterlock function itself. Theinterlock function isimplemented ashardwired logic andkeepsworking, evenifthe processor stops ortheprogram hangsup.Thesoftware performs asystem-test onpower-up, totest thehardware functionality and thecrateconfiguration. On success, theinterlock hardware gets configured foroperation andthecrateisputintotheworking state. Afterinitialization higher level applications getloaded. This covers thecommunication interface tothecontrol system anda diagnostic interface, whichisusedduring installation andtrouble shooting. Forthis purpose, LabVIEWtools areusedtopresent information. In addition, a HTTP Serveron theinterlock controller provides thepossibility tochangeconfiguration and viewactual status information. Italsoimplements tools which allow toreconfigure thewholeFPGAdesign ortoupload anew software version viaEthernet.