An analytical model of the overshooting effect for multiple-input gates in nanometer technologies

The overshooting effect, which is induced by the input-to-output coupling capacitance, has an significant effect on CMOS gate delay with the scaling of CMOS technology. In this paper, an effective analytical model is proposed to calculate the overshooting time of multiple-input gates. The proposed model is verified having a good agreement with SPICE simulation results.

[1]  Anas A. Hamoui,et al.  An analytical model for current, delay, and power analysis of submicron CMOS logic circuits , 2000 .

[2]  Atsushi Kurokawa,et al.  Modeling the Overshooting Effect for CMOS Inverter in Nanometer Technologies , 2007, 2007 Asia and South Pacific Design Automation Conference.

[3]  Atsushi Kurokawa,et al.  Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  D. Auvergne,et al.  A comprehensive delay macro modeling for submicrometer CMOS logics , 1999, IEEE J. Solid State Circuits.

[5]  Atsushi Kurokawa,et al.  Modeling the overshooting effect of multi-input gate in nanometer technologies , 2011, 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).

[6]  José Luis Rosselló,et al.  An analytical charge-based compact delay model for submicrometer CMOS inverters , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Philippe Maurine,et al.  Transition time modeling in deep submicron CMOS , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Jean Michel Daga,et al.  Signal transition time effect on CMOS delay evaluation , 2000 .

[9]  Labros Bisdounis,et al.  Analytical Modeling of Overshooting Effect in Sub-100 nm CMOS inverters , 2011, J. Circuits Syst. Comput..