Statistical Analysis and Design of HARP Routing Pattern FPGAs

Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. Th e routing architecture is designed to handle versatile conne ction configurations. However, providing such great flexibility comes at a high cost in terms of area, delay and power. We propose a new FPGA routing architecture that utilizes a mixture of hardwired and traditional flexible switches. The result is about 30% reduction in leakage power consumption, 5% smaller area and 20% shorter delays, which translates to 25% increase in clock frequency. Despite the increase in clock speeds, the o verall power consumption is reduced.

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