A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process
暂无分享,去创建一个
Kazumasa Yanagisawa | Koichiro Ishibashi | Yasuto Igarashi | Kazuo Otsuga | Sadayuki Morita | Masafumi Onouchi | Toyohito Ikeya | K. Ishibashi | K. Yanagisawa | K. Otsuga | Y. Igarashi | M. Onouchi | Toyohito Ikeya | S. Morita
[1] T. Karnik,et al. Area-efficient linear regulator with ultra-fast load regulation , 2005, IEEE Journal of Solid-State Circuits.
[2] Giuseppe Iannaccone,et al. A 2.6 nW, 0.45 V Temperature-Compensated Subthreshold CMOS Voltage Reference , 2011, IEEE Journal of Solid-State Circuits.
[3] Wing-Hung Ki,et al. A 0.9V 0.35 μm Adaptively Biased CMOS LDO Regulator with Fast Transient Response , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[4] Mohammad A. Al-Shyoukh,et al. A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer Impedance Attenuation , 2007, IEEE Journal of Solid-State Circuits.
[5] Anantha P. Chandrakasan,et al. A 0.16mm2 completely on-chip switched-capacitor DC-DC converter using digital capacitance modulation for LDO replacement in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).