AN EXPERIMENTAL l l n s 8K x 18 SRAM which incorporates advances in processing technology and circuit design will be discussed; Figures I, 2. Problems of making wide-data-path CMOS chips with tolerable noise and difficulties of interfacing next-generation technology chips with current technology have been resolved. The interface voltage levels are full TTL swings. The chip has a 3.6V power supply and uses 0.5pm channel lengths. Numerous parts with all 144K bits operational have been seen. An on-chip test circuit has been implemented t o aid in testing performance accuracy. The experimental fabrication technology is a 1 . 2 ~ N-well CMOS process with 14nm gate oxides. The nominal channel lengths for both PMOS and NMOS devices are 0.5pm and channel tolerances greater than 0.15pm have been seen while maintaining functionality’. A doubly-implanted lightly-doped drain (DILDD) was employed to minimize Vt rolloff and hotelectron impact on the time-zero Vt2. A six-device cell with an area of 2 3 5 ~ ~ ( 1 3 . 5 p x 17.4pm) was used. The overall chip size was 9.2mm x 6.5mm for a total chip area of 60mm2. The chip has circuit protection to allow input voltage swings to over 5V without damage to the receiver. This was implemented by placing an NMOS pass device in series with the gates of the receiver first stage. The driver is also protected in bidirectional applications; Figure 3 . A self-biasing N-well prevents latchup when the output node is forced higher than 3.6V. The VH supply is similarly gated by the output potential. Therefore, no dc current is drawn into the driver when its output has been tristated. An NMOS pass device is also used t o protect the pulldown circuitry from potentials of 5V or greater. With this design, there is no concern about hot carriers, latchup or snap back.