Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence

Electromigration (EM) greatly affects the long-term reliability of VLSI chips. Not only power/ground lines but also bitlines of SRAM arrays may be damaged by EM. In this paper, we analyze current flow on SRAM bitline, demonstrate that it may suffer EM due to the pulsed dc pattern, and conclude that bitline's EM reliability can dramatically be worsened by process variation due to a significant increase of subthreshold leakage current. We statistically model the effects of process variation that includes both transistor parameter fluctuation and interconnect line roughness, propose an atomic flux divergence-based current conversion scheme for applying Blech criterion, and develop a procedure for preventing EM failure by modifying the width of bitlines. Considering the effect of bitline width modification on cell stability and performance, we propose a tradeoff between functional and EM failures and indicate an optimal bitline width that maximizes the yield of SRAM arrays.

[1]  Ki-Don Lee.  Electromigration recovery and short lead effect under bipolar- and unipolar-pulse current , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[2]  T. Fukai,et al.  Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies , 2007, 2007 IEEE International Electron Devices Meeting.

[3]  Cher Ming Tan,et al.  Revisit to the finite element modeling of electromigration for narrow interconnects , 2007 .

[4]  Malgorzata Marek-Sadowska,et al.  Atomic flux divergence based current conversion scheme for signal line electromigration reliability assessment , 2014, IEEE International Interconnect Technology Conference.

[5]  Sani R. Nassif,et al.  Statistical analysis of SRAM cell stability , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[6]  A. Toriumi,et al.  Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFET's , 1994 .

[7]  Min Chen,et al.  Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[8]  Rob A. Rutenbar,et al.  Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Tsu-Jae King Liu,et al.  Advanced MOSFET Designs and Implications for SRAM Scaling Changhwan , 2011 .

[10]  P. Ho,et al.  Electromigration in metals , 1989 .

[11]  Xin Zhao,et al.  Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Paul S. Ho,et al.  Electromigration critical length effect in Cu/oxide dual-damascene interconnects , 2001 .

[13]  R. Wong,et al.  Impact of NBTI Induced Statistical Variation to SRAM Cell Stability , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

[14]  Yu Cao,et al.  New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration , 2006, IEEE Transactions on Electron Devices.

[15]  Carl V. Thompson,et al.  A hierarchical reliability analysis for circuit design evaluation , 1998 .

[16]  Malgorzata Marek-Sadowska,et al.  Statistical analysis of process variation induced SRAM electromigration degradation , 2014, Fifteenth International Symposium on Quality Electronic Design.

[17]  Kaustav Banerjee,et al.  Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[18]  Hamid Reza Naji,et al.  Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells , 2014, IEEE Transactions on Device and Materials Reliability.

[19]  Joan Figueras,et al.  Statistical analysis of 6T SRAM data retention voltage under process variation , 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

[20]  Chih-Hong Hwang,et al.  Process-variation- and random-dopant-induced static noise margin fluctuation in nanoscale CMOS and FinFET SRAM cells , 2009, 2009 1st Asia Symposium on Quality Electronic Design.

[21]  Zhong Guan,et al.  SRAM bit-line electromigration mechanism and its prevention scheme , 2013, International Symposium on Quality Electronic Design (ISQED).

[22]  C. Hu,et al.  An electromigration failure model for interconnects under pulsed and bidirectional current stressing , 1994 .

[23]  A. Afzali-Kusha,et al.  Process variation tolerant SRAM cell design using additive model considering NBTI effect , 2012, 2012 4th Asia Symposium on Quality Electronic Design (ASQED).

[24]  Jaijeet S. Roychowdhury,et al.  Rapid Estimation of the Probability of SRAM Failure due to MOS Threshold Variations , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[25]  R. Ramanujan,et al.  Hydrostatic stress and hydrostatic stress gradients in passivated copper interconnects , 2006 .

[26]  Jens Lienig,et al.  Electromigration and its impact on physical design in future technologies , 2013, ISPD '13.

[27]  Shyh-Chyi Wong,et al.  Modeling of interconnect capacitance, delay, and crosstalk in VLSI , 2000 .

[28]  Malgorzata Marek-Sadowska,et al.  Automatic Sizing of Power/Ground (P/G) Networks in VLSI , 1989, 26th ACM/IEEE Design Automation Conference.

[29]  I. Blech.  Electromigration in thin aluminum films on titanium nitride , 1976 .

[30]  K. Agarwal,et al.  Fast Characterization of Threshold Voltage Fluctuation in MOS Devices , 2008, IEEE Transactions on Semiconductor Manufacturing.

[31]  J. Black,et al.  Electromigration—A brief survey and some recent results , 1969 .